Introduction
Each applicant can apply for 2 positions simultaneously, please put your priority choice into “1st choice”, and we will handle your application form according to your 1st choice. If you fail for your 1st choice, your application form will go to our company talent pool for your 2nd choice position application. Please be very cautious about your “1st choice”.

Basic Requirements for all the posts:
• Master or above degree.
• Major in Micro-E or related, Electronic Engineer, Computer Science, Mathematics. Communication
• Have project experience during university education
• Proficient English and Mandarin (listening, writing and speaking).
• Strong passion in achievement and career development.
• A self-motivated team player.

GPU ASIC Design/Implementation Engineer
GPU ASIC Design Verification Engineer (SW& HW)
Multimedia ASIC Design Engineer
Multimedia ASIC Design Verification Engineer
GPU Driver Software Engineer
Chipset ASIC Design/ Design Verification Engineer

GPU ASIC Design/Implementation Engineer
Location:
Shanghai

Responsibility:
1. Develop micro-architecture specification for graphic engine
2. Develop RTL code for graphics engine in Verilog HDL
3. Responsible for Front-End chip implementation including design, implementation and
execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready
for physical design
4. Responsible for synthesis, netlist generation, timing and logical equivalency checks, and timing
constraint management

Requirement:
1. Familiar with Verilog HDL coding and ASIC Frond-End implementation flow
2. Familiar with unix/linux and scripts (tcl, perl, python etc.)
3. Strong task-based organization skills
4. Computer Architecture and computer Arithmatic(Plus)
5. Computer Graphic Basic knowledge(Plus)
GPU ASIC Design Verification Engineer (SW& HW)
Location:
Shanghai

Responsibility:
1. Modeling HW, do architecture/algorithm/design verification
2. Understand the architecture of 3D graphics chip and functional block being designed
3. Build simulation model
4. Compose test plan and validation vectors to ensure functional completeness according to the design specification

Requirement: (alternative)
For DV-Software,
1. Familiar with Computer Architecture, Arithmetic and Operating System
2. Good at c/c++, Makefile and script/shell programming
3. Familiar with unix/linux and scripts
4. Strong oral and written English and communication skills
5. Computer Graphic Basic knowledge (Plus)
6. Experience with design verification methodologies (Plus)

For DV-Hareware,
1. Solid Electronics background knowledge and Digital Design concept
2. Good at Verilog HDL coding and debugging
3. Familiar with unix/linux and scripts
4. Strong oral and written English and communication skills
5. Familiar with C or C++ programming
6. Familiar with SystemC and PLI (Plus)
7. Experience with design verification methodologies. (Plus)
Multimedia ASIC Design Engineer
Location:
Shanghai

Responsibility:
As an ASIC Designer at AMD design and implement the industry's leading Graphics, Video and Media & Communications Processors. Specific areas include mpeg, video, audio, display, PCI-Express, high-speed IO interfaces and memory subsystem design. You will be responsible for
1. Architecture and micro-architecture design of the ASICs,
2. RTL design and synthesis,
3. Logic and Timing verification using leading edge CAD tools and Semiconductor process technologies.

Requirement:
1. GPA of 8.0 out of 10.0 or higher is required
2. Familiar with complex high speed ASIC Design process.
3. Strong logic design, verification and debugging skills.
4. Relevant experience and knowledge in worldwide analog/IF demodulator, digital television standard ATSC/DVB-T/DVB-C, video decoder/audio decoder (NTSC/PAL, FM/AM/NICAM) research, algorithm, ASIC design and implementation (Plus)
5. Relevant experience in Memory Controller (DDR, DDR2, DDR3), Graphics, Video, Microprocessor Design, SOC design, or Multimedia ASIC designs (Plus)
6. Relevant experience in low power design (Plus)
7. Relevant experience in bus protocol USB/PCI design (Plus)
8. Relevant experience in high-speed system (PCIe/HT) design (Plus)
9. Relevant experience in video processing and display protocol DVI/ HDMI/ TV design (Plus)
10.Relevant experience in chip level design/integration, DFT, memBIST, Memory Compiler, STA (Plus)
11.Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, and C/C++ programming languages, CMOS transistors and circuits (Plus)
Multimedia ASIC Design Verification Engineer
Location:
Shanghai

Responsibility:
With increase in ASIC design complexity, verification becomes an important aspect of the design flow. The candidate will be working in the areas of multimedia ASIC / Display/ UVD/ PCI-Express design and verification. This position requires the candidate to work closely with the ASIC designers on
1. Understand the functional block being designed;
2. Compose test plan and validation vectors to ensure functional completeness according to the design specification;
3. Apply necessary verification methodologies to DUT;
4. Write BFM model and reference model;
5. Develop and maintain advanced test environments.

Requirements:
1. Familiar with at least one of C/C++ and Verilog, and have proper knowledge about another
2. Have experience of using Linux and programming under Linux
3. Familiar with theory of signal processing or encrypt/decrypt, or have plenty of project experience (Plus)
4. Strong background of display and video processing, or have plenty of project experience (Plus)
5. Strong background of PCI Express (Plus)
GPU Driver Software Engineer
Location:
Shanghai

Responsibility:
1. Design, implement and maintain AMD GPU driver software under both Microsoft Windows and Linux environment, including quality improvement and performance tuning
2. GPU Driver Software includes but not limited to following components

  • D3D. Provide the foundation for Microsoft DirectX 3D API. Only available under Microsoft Windows
    1) Work on Direct3D application, especially game’s performance tuning, including CrossFireX technologies
    2) Work on next generation DirectX technologies such as GPGPU and Tessellation
    3) Work on next generation Microsoft Windows. For example, Win7
    4) Work on AMD next generation GPU
    5) Improve and Maintain current driver with DX9/DX10 under Windows XP/Vista

  • OpenGL. Provide the foundation for OpenGL API. Available under both Microsoft Windows and Linux
    1) Work on OpenGL application, especially Workstation application’s performance tuning, including CrossFireX technologies
    2) Work on next generation OpenGL technologies such as OpenGL 3.0
    3) Work on next generation Microsoft Windows and Linux
    4) Work on AMD next generation GPU
    5) Improve and maintain current driver with OpenGL 1.x/2.0 under Windows XP/Vista and Linux

  • Display and Kernel drivers. Manage GPU HW resources and provide the foundation for D3D/OpenGL and other upper level components. Available under both Microsoft Windows and Linux
    1) Manage video memory, including system memory used by GPU
    2) Manage external devices driven by GPU
    3) Manage commands sent from upper level components to GPU
    4) Work on multiple GPU (MGPU) to provide technical foundation for CrossFireX
    5) Work on AMD next generation GPU
    6) Improve and maintain current driver, provide technical support to customer

    Requirement:
    1. Deep Knowledge of C/C++ programming
    2. Knowledge of Computer Graphics
    3. Knowledge of software driver developing under Microsoft Windows or Linux(Plus)
    4. Knowledge of x86 assembler language and x86/x64 CPU instructions(Plus)
    5. Knowledge of PC architecture
    6. Knowledge of Windows and Linux kernel(Plus)
    7. Knowledge of Object Oriented design(Plus)
    8. Knowledge of Microsoft DirectX and/or OpenGL and/or X server(Plus)
    9. Fluent English in reading, writing and speaking (Pass CET-6 as minimum or TOEIC top 30%)
    		•
    Chipset ASIC Design/ Design Verification Engineer
    Location:
    Shanghai

    Responsibility:
    The AMD South Bridges Group has openings for Design Verification Engineers and ASIC Designers. The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for Southbridge, the AMD Chipset.

    1. Work on the following tasks, specification, HDL coding, verification, synthesis, DFT assertion, timing closure, etc.
    2. FPGA implementation and debugging of some complex logic modules, may also need to help the lab PC system bring up or debugging.
    3. Work with a broad range of PC industry I/O interfaces and system chipset design techniques.

    Requirement:
    1. Solid background knowledge of electronics and semiconductor electronics
    2. Familiar with Digital system design and HDL language
    3. Familiar with ASIC flow and logic synthesis
    4. Familiar with C / C++
    5. Computer Architecture/Arithmetic (Plus)
    6. Complex Digital System design experience (Plus)
    7. BUS(PCI/PCI-e, USB, SATA, ARM, Gbit Ethernet) knowledge and design experience (Plus)
    8. Tapeout experience (Plus)
    9. Scripting/programming experience (Plus)
    由于很多同学下周一11月3日（AMD原定的笔试时间）当天有课，不能参加笔试。故AMD将笔试时间调整为本周日11月2日，特此通知。请同学们提前30分钟达到考场，谢谢配合。